Media Framework Engineer - Surrey UK
The successful candidate will be working in a small team, developing the media framework to support audio/video, playback/capture, on ZiiLABS ARM based media processors, under Android and Linux.
Responsibilities to Include:
- Developing ZiiLABS proprietary media framework to add value beyond the core Android functionality.
- Implementing media network protocols, video conferencing engines, media containers, handling A/V synch, interfacing to a range of codecs, supporting trick playback features, etc.
- Providing feedback to the chip architecture team to aid improvements in design.
Qualifications, Skills and Experience
- Excellent current 'C' and 'C++' programming.
- Experience of working with media frameworks.
- Strong debugging/fault finding skills.
- Experience of writing assembler for processor arrays and/or VLIW processors.
- Preferably a Software or Electronic Engineering Degree or equivalent (i.e. a Maths or Physics degree where the candidate has understanding of, or interest in, complex hardware systems).
The roles are based at our UK Design Centre in Surrey. Remuneration package will be commensurate with experience, and includes excellent basic salary, pension scheme, private health scheme, and life assurance.
Physical Design Team Leader - Surrey UK
We have an immediate requirement for a Physical Design Team Leader. The successful candidate would undertake physical design and verification of complex multi-media SOC ICs using leading-edge EDA tools. This is a very hands-on role that is challenging and can involve a high degree of responsibility for suitable applicants.
Responsibilities to Include:
- All levels of physical design (PD) from netlist to GDSII to tapeout
- Technical and line-management of the PD team
- Meeting all PD performance, power, and area targets for each SOC implementation
- Influencing the architecture-level and RTL-level design to ensure performance, power, and area targets can be met
- Scripted layout flow development to support multiple process/library options
- Working closely with EDA and IP suppliers to get best results from the PD flow
Qualifications, Skills and Experience
- Solid physical design experience is essential, ideally at 40nm and below
- Proven technical team leadership skills
- Physical design flow development, automation, and scripting
- Engineering Degree or equivalent background
Experience in any of the following would also be desirable
- Magma physical design and verification tools
- Physical verification - DRC/LVS
- Hierarchical PD including floorplanning and flip-chip IO design and verification
- Static timing analysis and timing closure problem solving
- Tool, library, and IP evaluation and selection
- High-speed interface/PHY implementation
The roles are based at our UK Design Centre in Surrey. Remuneration package will be commensurate with experience, and includes excellent basic salary, pension scheme, private health scheme, and life assurance.