Low Power HD Programmable Media Rich Processor

The ZMS-05 is a fully programmable, media-rich applications processor capable of delivering high-performance application, graphics and multimedia capabilities within a low-power environment.

The multi-core, System-on-Chip design combines a flexible media-processing array with dual ARM cores to achieve a fully balanced system for delivering the optimal acceleration of CPU and media-intensive tasks. Three fully featured video processing units provide glue-less connection to a wide range of displays and cameras. A broad range of I/Os and peripheral functions are fully integrated on-chip to ease system design and reduce overall system costs.

• Overview
• Block Diagram
• Performance
• Technical Specifications

HD Media and Graphics Processing

The HD media-processing array, based on ZiiLABS' unique stemcell computing architecture, offloads the ARM CPU to provide high-efficiency, multi-format video, graphics and image processing.

• High compute density SIMD architecture
• High resolution - decode to 1080p / 720p encode
• Simultaneous video encode/decode at D1
• Wide rage of optimised CODECs and APIs
• Accelerated OpenGL ES 3D graphics
• Hardware compositing
• Advanced image processing
• 8 GFlops programmable compute

ARM Core

The ARM subsystem, based on dual ARM926 EJ-S cores, provides high-performance, low-power application processing, leaving the media processing array to perform the heavy lifting media work.

Rich Peripheral Integration

A rich suite of integrated system peripherals and interfaces minimize overall system costs and design footprint;

• 64/32 bit memory interface
• Three bi-directional video units
• USB 2.0 controller
• Three SDIO/MMC/CE-ATA controllers
• HDTV out
• General interface supporting ethernet, NAND and NOR
• Serial connectivity
• Hi-Fidelity audio

Low-Energy

Total system power is minimized at all times by the application of advanced power management throughout the processor and supporting software and includes: dynamic clock and voltage scaling, independent power down regions, multiple clock domains and gating, and suspend to RAM.